Fundamentals of Non-Isolated Buck Converter

In dc-dc power converters, buck converter topology is often used to provide a regulated dc voltage to the load. An ideal switch mode buck converter is as shown in Fig. 1

Fig. 1 - Ideal switch model for DC-DC Buck converter

We will make the following assumptions for our analysis:

  • All the components are ideal
  • The converter operates in steady state
  • Capacitor is large enough to hold the output voltage constant
  • Inductor current is always positive, meaning the converter operates in continuous conduction mode (CCM)

Ideal switch can be realized using a MOSFET and a diode as shown in Fig. 2. Once again we will assume that the MOSFET and diode are ideal.

Fig. 2: Switch realization using MOSFET and Diode (top)
MOSFET ON, Diode reverse biased (middle)
MOSFET OFF, Diode forward biased (bottom)

Case I: MOSFET is ON

The diode will be reversed biased. The input voltage appears across the LC filter. The inductor current starts building up and the energy is transfered to charge the capacitor to built an output voltage. Let’s assume that M_1 is ON for time DT_s and OFF for (1-D)T_s=D'T_s, where D is the duty cycle.

Applying KVL across the loop,



L\frac{d}{dt} i_L(t)=V_g-V_0

\frac{d}{dt} i_L(t)=\frac{V_g-V_0}{L}

KCL at the output node gives,

i_L(t) = i_c(t) + \frac{V_0}{R}

i_c(t)=I_L - \frac{V_0}{R}


We know that the inductor current cannot go to 0 instantaneously. The energy stored in the inductor is used to keep the voltage constant across the capacitor. Here the diode is forward biased, and thus the loop can sustain the inductor current flow while discharging it. Applying KVL yields,



L\frac{d}{dt} i_L(t)=-V_0

\frac{d}{dt} i_L(t)=\frac{-V_0}{L}

 Applying KCL yields,

i_c(t)=I_L - \frac{V_0}{R}

The implication of assuming steady state condition is that the inductor current will be periodic. That is,


Inductor current,

i_L(t_0+T)=\frac{1}{L}\int^T_0 v_L (t) dt + i(t_0)

i_L(t_0+T)-i(t_0)=0=\frac{1}{L}\int^T_0 v_L(t) dt

Multiplying both sides by \frac{L}{T}

\frac{1}{T} \int^T_0 v_L(t) dt=0

Using inductor volt-second balance,


V_L*DT_s + V_L*(1-D)T_s=0

(V_g-V_0)*D + (-V_0)(1-D)=0



Conversion factor (Duty cycle),

D= \frac{V_0}{V_g}

Using capacitor charge balance,


(I_L-\frac{V_0}{R})*DT_s + (I_L-\frac{V_0}{R})*(1-D)T_s=0

(I_L - \frac{V_0}{R})*D + (I_L - \frac{V_0}{R}) - (I_L - \frac{V_0}{R})*D = 0


Thus, the average inductor current will be,


Let’s determine the ripple in the inductor current. We know that when M_1 is ON

\frac{d}{dt} i_L(t)=\frac{V_g-V_0}{L}

\frac{\Delta i_L}{\Delta t} = \frac{V_g-V_0}{L}

Since \Delta t corresponds to the time for which the MOSFET is ON, it can be replaced by DT_s. Thus the ripple in the inductor current is,

\Delta i_L=\frac{V_g-V_0}{L}DT_s=\frac{(1-D)V_0}{Lf_s}

Due to this ripple, the inductor current varies from a minimum to a maximum value

I_{L,max} = I_L + \frac{\Delta i_L}{2} = \frac{V_0}{R} + \frac{(1-D)V_0}{2Lf_s}

I_{L,min} = I_L - \frac{\Delta i_L}{2} = \frac{V_0}{R} + \frac{(1-D)V_0}{2Lf_s}

Fig. 3: Capacitor current waveform (top)
Inductor current waveform (bottom)

Similarly, the output voltage across the capacitor has a ripple imposed over it’s average value. This output voltage ripple is then determined using the charge equation for the capacitor. We know that the charge stored by a capacitor is given by,

q = C\Delta V

\Delta V = \frac{q}{C}

The change in capacitor voltage is attributed to the total positive charge stored by the capacitor. Looking at the capacitor current waveform in Fig. 3 we can determine the +ve charge stored by the capacitor, which is simply the area under the triangle.

\Delta Q = \left (\frac{1}{2}\right ) \left (\frac{\Delta i_L}{2}\right ) \left (\frac{T_s}{2}\right )

\Delta Q = \frac{1}{8} \left (\frac{(1-D)V_0}{Lf_s^2}\right )

Hence, the output voltage ripple is

\Delta V_0 = \frac{(1-D)V_0}{8LCf_s^2}

Using above equation we can make a good selection for the capacitance remembering that we want the capacitor to be as large as possible since its impedance will be negligible as compared to the load at higher operating frequencies, forcing majority of the inductor current ripple to bypass via the capacitor rather than the load. Similarly, we would want to choose inductor appropriate to required operation. One criteria that we might look at for CCM is that the inductor current must be positive. What if i_L goes to zero? In this case, we can write

I_{L,min} = 0

\frac{V_0}{R}=\frac{(1-D)V_0}{2L_{min} f_s}

L_{min} = \frac{(1-D)R}{2f_s}

The above result gives the minimum value of inductance so that the inductor current remains positive. In practice, one would like to choose inductance value 10 or 20 times higher than L_{min}. I will try to go over a design example for buck converter in upcoming posts.


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