First Project with Altera DE2-115

If anyone out there got an Altera DE2-115 development board, you must have realized that the quartus package bundled along with it is v10.1 or may be 11.1. Regardless, the fact of the matter is that if you do follow the tutorial and try to implement the “my_first_fpga” design, you will soon realize that some of the megafunctions in the newer edition of quartus are missing. This functions are definitely available on the previous 9.1 version of quartus II, albeit it does not provide support for the newer Cyclone IVE chip. I myself tried all pathways, eventually I just got stuck with everyone of them. So, I decided to create my own mux Verilog function in order to implement “my_first_fpga” design on my new board. Following is the Verilog function that I wrote in order to implement the aforementioned function. In order to create the functional block for adding it to the schematic diagram just follow the steps for simple_counter.v. Create the symbol using the File menu option and then insert it into the schematic.

Schematic

2 bus to 1 bus (4 bit each) MUX in Verilog

Here’s a video of the implementation on the DE2 board. Notice that the counter runs rapidly from 0000 to 1111. If you press and hold KEY0 then the counter progress slowly through the count.

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What does steady state operation mean for inductor and capacitor?

The implication of assuming steady state condition is that the inductor current will be periodic. That is,

i(t_0+T)=i(t_0)

Inductor current,

i_L(t_0+T)=\frac{1}{L}\int^T_0 v_L (t) dt + i(t_0)

i_L(t_0+T)-i(t_0)=0=\frac{1}{L}\int^T_0 v_L(t) dt

Multiplying both sides by \frac{L}{T}

\frac{1}{T} \int^T_0 v_L(t) dt=0

<v_L(t)>_{avg}=0

As we can see, the LHS is just the average inductor voltage. This is also known as the inductor volt-second balance which states that the average inductor voltage is 0 for periodic inductor current.

Similarly, for a capacitor in steady state, we can write

v_c(t_0+T)=v_c(t_0)

Capacitor voltage,

v_c(t_0+T)=\frac{1}{C} \int^{T+t_0}_{t_0} i_c(t)dt + v_c(t_0)

v_c(t_0+t)-v_c(t_0)=0=\frac{1}{C} \int^{T+t_0}_{t_0} i_c(t)dt

Multiplying both sides by \frac{C}{T}

\frac{1}{T} \int^{T+t_0}_{t_0} i_c(t)dt = 0

<i_c(t)>_{avg} = 0

Thus, under steady state condition, the average capacitor current is 0 over a cycle. This is also known as the capacitor charge balance.

CMOS NOR gate using dynamic logic

In order to implement the NOR gate, I have used dynamic logic using pull down network.

Implementation of dynamic logic using PDN

There are two phase of operation,

  1. Pre-charge phase – When the clock is low, the PMOS (Mp) is ON and the NMOS (Me) is OFF. So the capacitor at the output gets charged to Vdd, thus changing to logic 1.
  2. Evaluate phase – When the clock is high, Mp is OFF and Me is ON. The output capacitance gets discharged conditionally based on the logic function implemented by PDN, thus changing to logic 0.
NOR gate schematic

Implementation of NOR gate using dynamic logic

Simulation file for NOR gate

Simulation result

Note that the only combination of input when the output capacitor won’t get discharge is 0000, which you can notice when clock goes HIGH during the first cycle. For rest of the input combination, when the clocking signal is HIGH, the output is connected to ground and thus the capacitor has a resistive path for discharging.

CMOS 4 Input NAND Gate

Here’s my schematic and layout for a 4 input CMOS NAND gate. The dimensions of the devices are as follow:

I choose the width of the PMOS to be 4 micron since I wanted to minimize the delay for the worst case. The worst case scenario will be for the following combination of inputs:

  • Pull Up: 0111, 1011, 1101, 1110
  • Pull Down: 1111

In order to optimize for the worst case, we need to make the equivalent resistance of the pull up and pull down device equal for those input. For worst case pull down, we will have 4 NMOS in series to be ON. If we consider the resistance of a single NMOS to be Ron then for the worst case we get 4Ron.

4 input NAND gate schematic

Simulation file for the 4 input NAND gate

 

Simulation Result

4 input NAND gate layout

LVS check for the layout

 

 

An Overview of 3D Integrated Circuits

Since the invention of semiconductor devices, the silicon industry has seen innovation at a tremendous pace. Almost every two years, the number of transistors on a chip has roughly doubled as predicted by Gordon Moore in 1960s. In order to keep up this trend, the MOS devices have been aggressively scaled over the years, so that more and more transistors can be packed on chip. Although scaling at the microscopic level has limitations, and this has certainly created challenges for integrated circuit (IC) designers. Some of the issues which we face are power dissipation, clock distribution, noise, crosstalk, interconnects, just to name few. Day by day, these issues are hampering our progress to keep up with Moore’s law. As a result a paradigm shift is required to revolutionize the industry and keep up with the market demand. So, through this article, I wish to explore some of the alternatives which are being explored and put into practice. One such methodology is 3-Dimensional integration.

Until now, commercial electronic devices have planar ICs, meaning that all the devices are fabricated on the same silicon (Si) dye in a horizontal plane. The IC is divided into high level blocks and these blocks are interconnected through copper (Cu) interconnects. When the length of interconnect start increasing, the capacitance increases which in turn makes the device operate at slower speed due to increase in delay. One such area where this issue becomes evident is in memory arrays, where the word line (WL) and bit line (BL) gets longer and longer as the array size increases, which if not properly designed can lead into slower system memory. On the contrary, the market demands for faster products. The answer to this issue is once again 3D integration.
In a 3D IC, we try to take advantage of the vertical direction so that we can have devices fabricated on various silicon dye, which are then stacked together. Each layer communicates with its neighboring layer through interconnects running in vertical direction. So, we not only have interconnects network running in horizontal direction, but also in vertical direction as showing in fig. 1.

Fig. 1 - Schematic of a 3D chip

Fig. 2 - Implementation of SRAM in 3D

Fig. 2 shows how a SRAM block can be implemented in 3D integration. In doing so, we reduce the length of word lines as well as bit lines since they will be running vertically through shorter distance. In doing so, we achieve a faster memory block. The vertical interconnects can now be replaced by optical connections which provide larger bandwidth (BW) for on chip communication, thus avoiding buffer chains used to account for transmission line effect.

One such industrial methodology is 3D stacking implemented during the packaging stage. Fig. 3 shows a stack of 24 dyes. It uses copper wire bonding as stack interconnects (fig. 4) . As seen from fig. 3 the vertical interconnect density is limited to the peripheral region only. This limitation might affect the performance, as compared to using the entire surface area for vertical interconnects.

Fig. 3 - Stack of 24 chips

Fig. 4 - Copper Wire bonding for stack interconnect

With these advancements, we can not only achieve higher order of device integration, but also we can minimize the delay along the critical path by employing smarter integration techniques, thus providing better performance.

References:
[1] Saraswat, K.C.; , “3-D ICs: Motivation, performance analysis, technology and applications,” Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the , vol., no., pp.1-6, 5-9 July 2010
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , “3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,” Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001
[3] Akasaka, Y.; , “Three-dimensional IC trends,” Proceedings of the IEEE , vol.74, no.12, pp. 1703- 1714, Dec. 1986
[4] Amkor Technology, “3D & Stacked-Die Packaging Technology Solutions,”
[5] Amkor Technology, “Copper (Cu) Wire Bonding