Since the invention of semiconductor devices, the silicon industry has seen innovation at a tremendous pace. Almost every two years, the number of transistors on a chip has roughly doubled as predicted by Gordon Moore in 1960s. In order to keep up this trend, the MOS devices have been aggressively scaled over the years, so that more and more transistors can be packed on chip. Although scaling at the microscopic level has limitations, and this has certainly created challenges for integrated circuit (IC) designers. Some of the issues which we face are power dissipation, clock distribution, noise, crosstalk, interconnects, just to name few. Day by day, these issues are hampering our progress to keep up with Moore’s law. As a result a paradigm shift is required to revolutionize the industry and keep up with the market demand. So, through this article, I wish to explore some of the alternatives which are being explored and put into practice. One such methodology is 3-Dimensional integration.
Until now, commercial electronic devices have planar ICs, meaning that all the devices are fabricated on the same silicon (Si) dye in a horizontal plane. The IC is divided into high level blocks and these blocks are interconnected through copper (Cu) interconnects. When the length of interconnect start increasing, the capacitance increases which in turn makes the device operate at slower speed due to increase in delay. One such area where this issue becomes evident is in memory arrays, where the word line (WL) and bit line (BL) gets longer and longer as the array size increases, which if not properly designed can lead into slower system memory. On the contrary, the market demands for faster products. The answer to this issue is once again 3D integration.
In a 3D IC, we try to take advantage of the vertical direction so that we can have devices fabricated on various silicon dye, which are then stacked together. Each layer communicates with its neighboring layer through interconnects running in vertical direction. So, we not only have interconnects network running in horizontal direction, but also in vertical direction as showing in fig. 1.
Fig. 1 - Schematic of a 3D chip
Fig. 2 - Implementation of SRAM in 3D
Fig. 2 shows how a SRAM block can be implemented in 3D integration. In doing so, we reduce the length of word lines as well as bit lines since they will be running vertically through shorter distance. In doing so, we achieve a faster memory block. The vertical interconnects can now be replaced by optical connections which provide larger bandwidth (BW) for on chip communication, thus avoiding buffer chains used to account for transmission line effect.
One such industrial methodology is 3D stacking implemented during the packaging stage. Fig. 3 shows a stack of 24 dyes. It uses copper wire bonding as stack interconnects (fig. 4) . As seen from fig. 3 the vertical interconnect density is limited to the peripheral region only. This limitation might affect the performance, as compared to using the entire surface area for vertical interconnects.
Fig. 3 - Stack of 24 chips
Fig. 4 - Copper Wire bonding for stack interconnect
With these advancements, we can not only achieve higher order of device integration, but also we can minimize the delay along the critical path by employing smarter integration techniques, thus providing better performance.
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 Amkor Technology, “3D & Stacked-Die Packaging Technology Solutions,”
 Amkor Technology, “Copper (Cu) Wire Bonding”